THM_TMON0_RDIL5_DATA__Z__SHIFT  391 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000
THM_TMON0_RDIL5_DATA__Z__SHIFT 4202 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT 4192 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT 3410 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT 4324 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT 4022 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT  200 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT                                                                        0x0
THM_TMON0_RDIL5_DATA__Z__SHIFT  344 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h #define THM_TMON0_RDIL5_DATA__Z__SHIFT                                                                        0x0