TDC_VRM_LIMIT__IDD__SHIFT 2510 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
TDC_VRM_LIMIT__IDD__SHIFT 2616 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
TDC_VRM_LIMIT__IDD__SHIFT 2614 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
TDC_VRM_LIMIT__IDD__SHIFT 2774 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
TDC_VRM_LIMIT__IDD__SHIFT  902 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
TDC_VRM_LIMIT__IDD__SHIFT  930 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define TDC_VRM_LIMIT__IDD__SHIFT 0x0