TDC_MV_AVERAGE__IDD__SHIFT 2414 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
TDC_MV_AVERAGE__IDD__SHIFT 2612 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
TDC_MV_AVERAGE__IDD__SHIFT 2610 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
TDC_MV_AVERAGE__IDD__SHIFT 2770 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
TDC_MV_AVERAGE__IDD__SHIFT  898 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
TDC_MV_AVERAGE__IDD__SHIFT  926 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define TDC_MV_AVERAGE__IDD__SHIFT 0x0