TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 9105 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT                                                                0x10
TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 10632 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT                                                                0x10