TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 9078 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 10605 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 10435 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 10645 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 13608 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 15538 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 16108 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10