TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 9390 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK                                                                  0x0000000CL
TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 10913 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK                                                                  0x0000000CL