TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 9389 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK                                                                 0x00000003L
TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 10912 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK                                                                 0x00000003L