TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 3034 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 4472 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 4664 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 3648 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 4768 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 4672 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4