SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 3579 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 55946 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L
SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 39784 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L
SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 75219 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L
SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 44425 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L