SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 3404 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 55746 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b
SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 39456 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b
SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 74891 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b
SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 44232 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b