SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 3406 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 55747 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c
SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 39457 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c
SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 74892 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c
SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 44233 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c