SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 8200 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 3253 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 3103 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L