SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 8196 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 3249 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 3099 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L