SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 8194 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 3247 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 3097 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L