SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 3487 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 3337 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 3205 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 8718 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 12249 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 14097 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 14495 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff