SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 3477 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 3327 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 3195 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 8711 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 12242 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 14090 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 14488 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0