SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 2593 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10
SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 2443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10