SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 2582 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK                                                         0x0C000000L
SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 2432 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK                                                         0x0C000000L