SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 23725 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 16323 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 17654 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 17529 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 7687 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 8720 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 10322 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 10720 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0