SPI_PS_IN_CONTROL__NUM_INTERP_MASK 23731 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 16328 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 17659 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 17534 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 7686 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 8719 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 10321 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
SPI_PS_IN_CONTROL__NUM_INTERP_MASK 10719 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f