SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 8489 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000060L
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 20357 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 21690 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 21620 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 7484 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 9251 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 10971 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 11369 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40