SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  253 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  350 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  346 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  346 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  348 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  346 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT  374 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3