SMB_CSR            81 arch/mips/sibyte/swarm/rtc_m41t81.c #define SMB_CSR(reg)	IOADDR(A_SMB_REGISTER(1, reg))
SMB_CSR            56 arch/mips/sibyte/swarm/rtc_xicor1241.c #define SMB_CSR(reg)	IOADDR(A_SMB_REGISTER(1, reg))
SMB_CSR            24 drivers/i2c/busses/i2c-sibyte.c #define SMB_CSR(a,r) ((long)(a->reg_base + r))
SMB_CSR          1027 drivers/net/ethernet/marvell/sky2.h 	SMB_CSR		 = 0x0e44, /* 32 bit	SMBus Control/Status Register */