SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  210 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  222 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  216 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  342 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  951 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT                                                                   0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  945 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT                                                                   0x4
SEM_STATUS__WRITE1_FIFO_FULL__SHIFT  973 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT                                                                   0x4