SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  222 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  234 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  228 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  354 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  957 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT                                                                0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  951 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT                                                                0xa
SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT  979 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT                                                                0xa