SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  220 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  232 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  226 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  352 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  956 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT                                                              0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  950 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT                                                              0x9
SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT  978 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT                                                              0x9