SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  218 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  230 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  224 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  350 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  955 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT                                                              0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  949 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT                                                              0x8
SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT  977 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT                                                              0x8