SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  228 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  240 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  234 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  360 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  960 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT                                                               0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  954 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT                                                               0xd
SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT  982 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT                                                               0xd