SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  226 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  238 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  232 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  358 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  959 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT                                                               0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  953 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT                                                               0xc
SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT  981 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT                                                               0xc