SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT  839 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT  254 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT  272 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT  270 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT  394 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 1020 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT                                                           0x0
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 1014 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT                                                           0x0
SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 1042 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT                                                           0x0