SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  835 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  242 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  256 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  254 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  378 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 1003 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT                                                          0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT  997 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT                                                          0xf
SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 1025 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT                                                          0xf