SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT  240 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT  254 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT  252 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT  376 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 1002 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT                                                         0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT  996 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT                                                         0xc
SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 1024 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT                                                         0xc