SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT  244 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT  258 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT  256 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT  380 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 1004 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT                                                        0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT  998 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT                                                        0x12
SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 1026 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT                                                        0x12