SEM_EDC_CONFIG__DIS_EDC__SHIFT  230 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT  244 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT  242 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT  366 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT 1233 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT                                                                        0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT 1184 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT                                                                        0x1
SEM_EDC_CONFIG__DIS_EDC__SHIFT 1288 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define SEM_EDC_CONFIG__DIS_EDC__SHIFT                                                                        0x1