SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 3254 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  768 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT	0xb
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  786 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT  782 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb