SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 3253 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  759 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT	0x2
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  777 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT  773 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2