SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 3267 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  780 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT	0x19
SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  798 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT  794 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19