SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 3268 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  778 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT	0x15
SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  796 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT  792 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15