SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 2973 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 1456 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 1616 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 2134 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 2438 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT  493 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT	0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT  495 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
SDMA1_STATUS_REG__SRBM_IDLE__SHIFT  491 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe