SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 2985 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 1476 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 1640 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 2158 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 2462 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT  505 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT	0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT  503 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c