SDMA1_STATUS_REG__SEM_IDLE__SHIFT 2983 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT 1472 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT 1636 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT 2154 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT 2458 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT  503 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT	0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT  505 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
SDMA1_STATUS_REG__SEM_IDLE__SHIFT  501 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a