SDMA1_STATUS_REG__REG_IDLE__SHIFT 2960 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT 1430 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT 1590 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT 2108 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT 2412 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT  480 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT	0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT  482 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
SDMA1_STATUS_REG__REG_IDLE__SHIFT  478 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1