SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 2972 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 1454 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 1614 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 2132 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 2436 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT	0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT  494 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT  490 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd