SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 2981 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 1468 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 1632 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 2150 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 2454 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 501 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 503 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 499 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16