SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 2978 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 1464 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 1626 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 2144 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 2448 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT  498 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT	0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT  500 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT  496 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13