SDMA1_STATUS_REG__INT_IDLE_MASK 3015 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
SDMA1_STATUS_REG__INT_IDLE_MASK 1477 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
SDMA1_STATUS_REG__INT_IDLE_MASK 1641 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
SDMA1_STATUS_REG__INT_IDLE_MASK 2159 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
SDMA1_STATUS_REG__INT_IDLE_MASK 2463 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
SDMA1_STATUS_REG__INT_IDLE_MASK  535 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK	0x40000000L
SDMA1_STATUS_REG__INT_IDLE_MASK  537 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
SDMA1_STATUS_REG__INT_IDLE_MASK  533 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L