SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 2977 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 1462 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 1624 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 2142 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 2446 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT  497 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT	0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT  499 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT  495 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12