SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 2965 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 1440 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 1600 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 2118 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 2422 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT  485 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT	0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT  487 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT  483 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6