SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 2966 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 1442 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 1602 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 2120 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 2424 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT	0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT  488 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT  484 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7