SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 2970 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 1450 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 1610 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 2128 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 2432 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT  490 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT	0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT  488 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb